Adopts PCI-E X4 design integrated 4-RJ45 ports specially designed for server and high-end devices; With function of hardware acceleration checking TCP / UDP / IP and segmenting TCP; Each port can send and receive eight queues; Supports SR-IOV; Supports 8 pool (single queue) VMDq of each port; Support DCA; Supports Intel I / O acceleration technology v3.0; UDP and TCP send TSO; SCTP receives and sends check and offload; Packet timer and delay timer are working for sending and receiving; Supports PCI Express 2.0 (5 GTs); Packet buffer based on each channel can reduce use of CPU; Reliable safe and power-saving.Intel MAC + PHY 82580 double integration and SERDES chip controller with high performance high reliability and low power consumption characteristics. Super depth based on the packet buffer per channel can reduce the use of the CPU. Hardware acceleration can be partial load task from the main processor. The controller can be used for partial load TCP/UDP/IP checksum TCP segment. Server level of reliability availability and performance characteristics: Link aggregation and load balancing. Relevant switches: 802.3 AD (LACP) common Trunking (GEC/FEC). Exchange and NIC no related. Failover. Prioritization - 802.1 p layer 2 priority coding. Adopts PCI-E X4 design integrated 4-RJ45 ports specially designed for server and high-end devices; With function of hardware acceleration checking TCP / UDP / IP and segmenting TCP; Each port can send and receive eight queues; Supports SR-IOV; Supports 8 pool (single queue) VMDq of each port; Support DCA; Supports Intel I / O acceleration technology v3.0; UDP and TCP send TSO; SCTP receives and sends check and offload; Packet timer and delay timer are working for sending and receiving; Supports PCI Express 2.0 (5 GTs); Packet buffer based on each channel can reduce use of CPU; Reliable safe and power-saving. Large frame (9.5 KB). 802 x flow control. Multicast/broadcast packet replication.